1. Field of the Invention
This invention relates to delay circuits within an integrated circuit placed within a signal path to compensate for a delay difference of the signal path with another signal path to appropriately align arrival of signals on the separate signal paths. More particularly, this invention relates to delay circuits that have delays that are generally independent of the voltage level of the signals on the signal path.
2. Description of the Related Art
An integrated circuit is formed of many circuits performing sets of interdependent functions. For instance, in a Dynamic Random Access Memory (DRAM) the address signals arrive at a decode function to select the desired memory cell or cells to be read from or written to. At appropriate timing intervals the control signals, such as Row Address Strobe (RAS), Column Address Strobe (CAS), Chip Enable (CE), and clock, arrive at a control function that will generate the appropriate timing signals necessary to gate the word-line activation signals (WL.sub.n) to place a word-line signal on a desired row of an array of memory cells. The row of memory cells is activated, and in a read operation, a charge present within the memory cell flows to an attached bit-line. The voltage level present on the bit-line is determined by the level of charge within the memory cell. To sense the voltage level on a bit-line a sense amplifier must be activated at the correct time to sense the voltage level of the bit-line to determine the state of the data retained in the memory cell. The signals that activate the word-line decoder and the bit-line sense amplifier have a common initiation, but must occur at separate times. The timing for the two paths becomes critical.
One of the factors that influence the relative occurrence of the two signals is the voltage level of each signal. In one instance, the delay for one path, for example, the word-line decode and word-line activation, may be naturally insensitive to the voltage level of the signals traversing the path. However, the delay of the second path, in this case the sense line activation signal, may be dependent upon the voltage level of the signal.
Refer now to FIG. 1 for a general discussion of the impact of the differences in delay of two signals. In FIG. 1, a first signal V.sub.1 traverses a first delay circuit DC.sub.1, and a second signal V.sub.2 traverses a second delay circuit DC.sub.2. The delayed version of the first signal V.sub.1 d and the delayed version of the second signal V.sub.2 d are combined in the functional block F1 according to the function V.sub.0 =H(V.sub.1, V.sub.2). Any variations in the delay of the first delay circuit DC.sub.1, or second delay circuit DC.sub.2 due to voltage variations (either the power supply voltage level or the voltage levels of the first signal V.sub.1 or the second signal V.sub.2 affect the results of the output voltage V.sub.0 of the functional circuit F1.
Refer to FIG. 2 for further explanation of this effect. In FIG. 2, the delay of the first delay circuit DC.sub.1 is designated d1 and the delay of the second delay circuit DC.sub.2 is designated d.sub.2. If the first delay is essentially dependent only on such parameters as the line resistance and parasitic capacitances such as for the word-lines and bit-lines of a DRAM memory array, the delay is relatively constant and can be accounted for. However, if the second delay circuit DC.sub.2 is an active delay circuit used to compensate in the differences in time between the first signal V.sub.1, and the second signal V.sub.2, the second delay d.sub.2 as explained hereinafter has a dependency on the voltage level of the second signal V.sub.2. When the variation in the voltage level of the second signal V.sub.2 is too great, the delay d.sub.2 of the second delay circuit may vary so as to corrupt the output voltage V.sub.0. In the example of a DRAM, the second delay circuit is an active delay circuit used to delay the sense amplifier activation signal until the voltage level on the bit-lines is set to indicate the level of charge present on the memory cell. If the voltage level of the original sense amplifier activation signal varies, then the magnitude of the delay time d.sub.2 varies and the sense amplifier may sense the incorrect data.
Refer now to FIG. 3 for a description of an active delay circuit. The basic active delay circuit consists of two inverters connected serially with the output of the first inverter I.sub.1 connected to the input of the second inverter I.sub.2. The capacitor C.sub.1 is connected to the junction of the output of the first inverter I.sub.1 and the input of the second inverter I.sub.2. The input of the first inverter I.sub.1, receives the input signal V.sub.IN. The output A of the first inverter I.sub.1 provides a voltage signal that is the inverse of the input signal V.sub.IN The transition time of the output A of the first inverter I.sub.1, is determined by the value of the capacitor C.sub.1.
The voltage level of the output V.sub.0 at the second inverter I.sub.2 is the inverse of the voltage level at the input of the second inverter I.sub.2. The threshold at which the output V.sub.OUT of the second inverter transitions between voltage levels is thus delayed by the change in transition time determined by the value of the capacitor C.sub.1.
The inverters I.sub.1 and I.sub.2 of FIG. 3a are generally structured as shown in FIG. 3b. The input terminal of the inverter is connected to the gates of the p-type metal oxide semiconductor (MOS) transistor P.sub.1 and n-type (MOS) transistor N.sub.1. The source of the p-type MOS transistor P.sub.1 is connected to the power supply voltage source V.sub.DD, and the source of the n-type MOS transistor N.sub.1 is connected to the ground reference point. The drains of the p-type MOS transistor P.sub.1 and the n-type MOS transistor N.sub.1 are connected together to form the output terminal of the inverter. The output terminal is connected to a load capacitor C.sub.L that simulates the wiring capacitances and input capacitances of subsequent circuits.
The output voltage V.sub.CL at the output terminal during a transition from a low voltage level to a high voltage level is determined by the formula: ##EQU1##
where: PA1 where:
Q is the charge present on the load capacitor. PA2 C.sub.L is the value of the load capacitor. PA2 t is the time of the transition of the output signal. PA2 I.sub.DSP is the drain-to-source saturation current of the p-type MOS transistor P.sub.1 and is proportional to the square of the input voltage V.sub.IN. That is: EQU I.sub.DSN =(V.sub.DD -V.sub.IN(L)).sup.2. PA2 I.sub.DSN is the drain-to-source saturation current of the n-type MOS transistor N.sub.1 and is also proportional to the square of the input voltage V.sub.IN. That is:
Likewise, the voltage V.sub.CL at the output terminal during a transition from a high voltage level to a low voltage level is determined by the formula: ##EQU2##
I.sub.DSN =V.sub.IN(L).sup.2 =V.sub.DD.sup.2 PA3 because V.sub.in =V.sub.DD when V.sub.in high.
FIG. 4 illustrates the plots of the waveforms at the input terminal V.sub.IN of the first inverter I.sub.1, the output A of the first inverter I.sub.1 and the output V.sub.OUT of the second inverter I.sub.2. As described above, the output A of the first inverter I.sub.1 has a transition from a high voltage level to a low voltage level that is proportional to the drain-to-source saturation current of the n-type MOS transistor N.sub.1 and thus proportional to the square of the input voltage level V.sub.IN. A variation in the voltage level of the input voltage V.sub.IN causes a variation in the delay d.sub.3 between the transition of the input voltage level V.sub.IN and the output voltage level V.sub.OUT.
Likewise, the output A of the first inverter I.sub.1 has a transition from a low voltage level to a high voltage level that is proportional to the drain-to-source saturation current of the p-type MOS transistor P.sub.1 and thus proportional to the square of the difference between the power supply voltage source V.sub.DD and the input voltage level V.sub.IN. Also, as stated above, any variation in the voltage level of the input voltage level V.sub.IN causes a variation in the delay between the transition of the input voltage level V.sub.IN and the output voltage level V.sub.OUT.
As described in FIG. 1, any variation in the delays d.sub.3 and d.sub.4 will affect the output signal of the functional circuit F.sub.1 and thus may cause error conditions. In a DRAM this error, condition may be a misreading of the data transferred from a memory cell.
U.S. Pat. No. 5,317,219 and U.S. Pat. No. 5,175,452 (Lupi, et al.) each describe a programmable compensated digital delay circuit. A signal-to-be-delayed is provided to a group of time delay cells which, are selectively capable of being interconnected, thus forming one or more delay configurations. In each delay cell, selectable capacitive elements are arrayed in a weighted manner and a memory programmably selects the capacitive elements by switching differently rated capacitive elements into and out of the circuit. Selectable current sources are arrayed in a weighted manner, and another memory programmably selects the current sources by switching differently rated current sources into and out of the circuit. The delay circuit includes internal compensation and uses a ring oscillator for temperature and power supply compensation. A pulse-width distortion compensation device is provided to compensate the delay line for switching non-linearities. The pulse-width compensation portion of the device serially connects an even number of complementary delay elements to cancel transfer function deviations.
U.S. Pat. No. 5,300,837 (Fischer) teaches a delay compensation technique for buffers. An integrated circuit has a signal path including a first circuit that introduces a propagation delay that decreases with circuit conditions and process speed in series with a second circuit that introduces a propagation delay that increases with circuit conditions and process speed. The circuit conditions and process speed are sensed and the duration of the propagation delay of the second circuit varied such that the total propagation delay remains within a predetermined range over circuit condition and process speed variations.
U.S. Pat. No. 5,315,550 (Tobita) describes a dynamic random access memory having sense amplifier activation delayed based on operation supply voltage. The dynamic random access memory operates with different power supply voltages and provides sufficient operating margin for each rated voltage. The dynamic random access memory comprises a circuit for generating a signal for defining operation speed/timing of a sense amplifier depending on the operation supply voltage, and a circuit for driving the sense amplifier in response to an output of a defining signal generating circuit.